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MOTOROLA

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

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by MC145483/D

3 V 13-Bit Linear PCM

Codec-Filter

The MC145483 is a 13–bit linear PCM Codec–Filter with 2s complement data

format, and is offered in 20–pin SOG, SSOP, and TSSOP packages, and a

32–pin QFN package. This device performs the voice digitization and

reconstruction as well as the band limiting and smoothing required for the voice

coding in digital communication systems. This device is designed to operate in

both synchronous and asynchronous applications and contains an on–chip

precision reference voltage.

This device has an input operational amplifier whose output is the input to the

encoder section. The encoder section immediately low–pass filters the analog

signal with an active R–C filter to eliminate very high frequency noise from being

modulated down to the passband by the switched capacitor filter. From the

active R–C filter, the analog signal is converted to a differential signal. From this

point, all analog signal processing is done differentially. This allows processing

of an analog signal that is twice the amplitude allowed by a single–ended

design, which reduces the significance of noise to both the inverted and

non–inverted signal paths. Another advantage of this differential design is that

noise injected via the power supplies is a common–mode signal that is

cancelled when the inverted and non–inverted signals are recombined. This

dramatically improves the power supply rejection ratio.

After the differential converter, a differential switched capacitor filter band–

passes the analog signal from 200 Hz to 3400 Hz before the signal is digitized

by the differential 13–bit linear A/D converter. The digital output is 2s

complement format.

The decoder digital input accepts 2s complement data and reconstructs it

using a differential 13–bit linear D/A converter. The output of the D/A is

low–pass filtered at 3400 Hz and sinX/X compensated by a differential switched

capacitor filter. The signal is then filtered by an active R–C filter to eliminate the

out–of–band energy of the switched capacitor filter.

The MC145483 PCM Codec–Filter has a high–impedance VAG reference pin

which allows for decoupling of the internal circuitry that generates the

mid–supply VAG reference voltage to the VSS power supply ground. This

reduces clock noise on the analog circuitry when external analog signals are

referenced to the power supply ground.

The MC145483 13–bit linear PCM Codec–Filter accepts both Short Frame

Sync and Long Frame Sync clock formats, and utilizes CMOS due to its reliable

low–power performance and proven capability for complex analog/digital VLSI

functions.

•

Single 3 V Power Supply

13–Bit Linear ADC/DAC Conversions with 2s Complement Data Format

Typical Power Dissipation of 8 mW, Power–Down of 0.01 mW

Fully–Differential Analog Circuit Design for Lowest Noise

Transmit Band–Pass and Receive Low–Pass Filters On–Chip

Transmit High–Pass Filter May be Bypassed by Pin Selection

Active R–C Pre–Filtering and Post–Filtering

On–Chip Precision Reference Voltage of 0.886 V for a – 5 dBm TLP

@ 600

Ω

•

3–Terminal Input Op Amp Can be Used, or a 2–Channel Input Multiplexer

•

Receive Gain Control from 0 dB to – 21 dB in 3 dB Steps in Synchronous

Operation

•

Push–Pull 300–Ω Power Drivers with External Gain Adjust

MC145483

DW SUFFIX

SOG PACKAGE

CASE 751D

SD SUFFIX

SSOP

CASE 940C

Freescale Semiconductor, Inc...

DT SUFFIX

TSSOP

CASE 948E

FC SUFFIX

QFN

CASE 1311

ORDERING INFORMATION

MC145483DW

MC145483SD

MC145483DT

MC145483FC

SOG Package

SSOP

TSSOP

QFN

REV 3

4/2003

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MC145483

Freescale Semiconductor, Inc.

PIN ASSIGNMENTS

20-PIN

SOG, SSOP, and TSSOP

Ref

RO–

PO–

PO+

FSR

BCLKR

PDI

TI+

TI–

FST

BCLKT

MCLK

32-PIN

QFN

RO–

Ref

TI+

PO–

PO+

FSR

BCLKR

PDI

MCLK

BCLKT

TI–

FST

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RECEIVE

SHIFT

RO –

–

SHARED

DAC

PO +

VDD

VSS

VAG Ref

–1

VDD

0.886 V

REF

VSS

SEQUENCE

AND

CONTROL

FSR

BCLKR

PDI

MCLK

BCLKT

FST

FREQ

DAC

PO –

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VAG

TI –

TI +

–

FREQ

ADC

TRANSMIT

SHIFT

Figure 1. MC145483 13–Bit Linear PCM Codec–Filter Block Diagram

DEVICE DESCRIPTION

A PCM Codec–Filter is used for digitizing and reconstruct-

ing the human voice. These devices are used primarily for

the telephone network to facilitate voice switching and trans-

mission. Once the voice is digitized, it may be switched by

digital switching methods or transmitted long distance (T1,

microwave, satellites, etc.) without degradation. The name

codec is an acronym from ‘‘COder’’ for the analog–to–digital

converter (ADC) used to digitize voice, and ‘‘DECoder’’ for

the digital–to–analog converter (DAC) used for reconstruct-

ing voice. A codec is a single device that does both the ADC

and DAC conversions.

To digitize intelligible voice requires a signal–to–distortion

ratio of about 30 dB over a dynamic range of about 40 dB.

This may be accomplished with a linear 13–bit ADC and

DAC. The MC145483 satisfies these requirements and may

be used as the analog front–end for voice coders using DSP

technology to further compress the digital data stream.

In a sampling environment, Nyquist theory says that to

properly sample a continuous signal, it must be sampled at a

frequency higher than twice the signal’s highest frequency

component. Voice contains spectral energy above 3 kHz, but

its absence is not detrimental to intelligibility. To reduce the

digital data rate, which is proportional to the sampling rate, a

sample rate of 8 kHz was adopted, consistent with a band-

width of 3 kHz. This sampling requires a low–pass filter to

limit the high frequency energy above 3 kHz from distorting

the in–band signal. The telephone line is also subject to

50/60 Hz power line coupling, which must be attenuated

from the signal by a high–pass filter before the analog–to–

digital converter. The MC145483 includes a high–pass filter

for compatibility with existing telephone applications, but it

may be removed from the analog input signal path by the

high–pass bypass pin.

The digital–to–analog conversion process reconstructs a

staircase version of the desired in–band signal, which has

spectral images of the in–band signal modulated about the

sample frequency and its harmonics. These spectral images

are called aliasing components, which need to be attenuated

to obtain the desired signal. The low–pass filter used to at-

tenuate these aliasing components is typically called a re-

construction or smoothing filter.

The MC145483 PCM Codec–Filter has the codec, both

presampling and reconstruction filters, and a precision volt-

age reference on–chip.

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MC145483

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PIN DESCRIPTIONS

POWER SUPPLY

VDD

Positive Power Supply (Pin 6)

This is the most positive power supply and is typically con-

nected to + 3 V. This pin should be decoupled to VSS with a

0.1

µF

ceramic capacitor.

VSS

Negative Power Supply (Pin 15)

This is the most negative power supply and is typically

connected to 0 V.

VAG

Analog Ground Output (Pin 20)

when a logic 1 is applied to this pin. The device goes through

a power–up sequence when this pin is taken to a logic 1

state, which prevents the DT PCM output from going low im-

pedance for at least two FST cycles. The VAG and VAG Ref

circuits and the signal processing filters must settle out be-

fore the DT PCM output or the RO– receive analog output

will represent a valid analog signal.

ANALOG INTERFACE

TI+

Transmit Analog Input (Non–Inverting) (Pin 19)

This is the non–inverting input of the transmit input gain

setting operational amplifier. This pin accommodates a differ-

ential to single–ended circuit for the input gain setting op

amp. This allows input signals that are referenced to the V SS

pin to be level shifted to the VAG pin with minimum noise.

This pin may be connected to the VAG pin for an inverting

amplifier configuration if the input signal is already refer-

enced to the VAG pin. The common mode range of the TI+

and TI– pins is from 1.2 V, to V DD minus 1.2 V. This is an FET

gate input.

The TI+ pin also serves as a digital input control for the

transmit input multiplexer. Connecting the TI+ pin to V DD will

place this amplifier’s output (TG) into a high–impedance

state, and selects the TG pin to serve as a high–impedance

input to the transmit filter. Connecting the TI+ pin to VSS will

also place this amplifier’s output (TG) into a high–impedance

state, and selects the TI– pin to serve as a high–impedance

input to the transmit filter.

TI–

Transmit Analog Input (Inverting) (Pin 18)

This is the inverting input of the transmit gain setting op-

erational amplifier. Gain setting resistors are usually con-

nected from this pin to TG and from this pin to the analog

signal source. The common mode range of the TI+ and TI–

pins is from 1.2 V to VDD – 1.2 V. This is an FET gate input.

The TI– pin also serves as one of the transmit input mulit-

plexer pins when the TI+ pin is connected to VSS. When TI+

is connected to VDD, this pin is ignored. See the pin descrip-

tions for the TI+ and the TG pins for more information.

Transmit Gain (Pin 17)

This is the output of the transmit gain setting operational

amplifier and the input to the transmit band–pass filter. This

op amp is capable of driving a 2 kΩ load. Connecting the TI+

pin to VDD will place the TG pin into a high–impedance state,

and selects the TG pin to serve as a high–impedance input to

the transmit filter. All signals at this pin are referenced to the

VAG pin. When TI+ is connected to VSS, this pin is ignored.

See the pin descriptions for TI+ and TI– pins for more in-

formation. This pin is high impedance when the device is in

the powered–down mode.

RO–

Receive Analog Output (Inverting) (Pin 2)

This is the inverting output of the receive smoothing filter

from the digital–to–analog converter. This output is capable

of driving a 2 kΩ load to 0.886 V peak referenced to the VAG

pin. If the device is operated half–channel with the FST pin

clocking and FSR pin held low, the receive filter input will be

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This output pin provides a mid–supply analog ground. This

pin should be decoupled to VSS with a 0.01

µF

ceramic ca-

pacitor. All analog signal processing within this device is ref-

erenced to this pin. If the audio signals to be processed are

referenced to V SS, then special precautions must be utilized

to avoid noise between V SS and the VAG pin. Refer to the ap-

plications information in this document for more information.

The VAG pin becomes high impedance when this device is in

the powered–down mode.

VAG Ref

Analog Ground Reference Bypass (Pin 1)

This pin is used to capacitively bypass the on–chip circuit-

ry that generates the mid–supply voltage for the VAG output

pin. This pin should be bypassed to VSS with a 0.1

µF

ceram-

ic capacitor using short, low inductance traces. The VAG Ref

pin is only used for generating the reference voltage for the

VAG pin. Nothing is to be connected to this pin in addition to

the bypass capacitor. All analog signal processing within this

device is referenced to the VAG pin. If the audio signals to be

processed are referenced to VSS, then special precautions

must be utilized to avoid noise between VSS and the VAG pin.

Refer to the applications information in this document for

more information. When this device is in the powered–down

mode, the VAG Ref pin is pulled to the VDD power supply with

a non–linear, high–impedance circuit.

CONTROL

Transmit High–Pass Filter Bypass (Pin 16)

This pin selects whether the transmit high–pass filter will

be used or bypassed, which allows frequencies below

200 Hz to appear at the input of the ADC to be digitized. This

high–pass filter is a third order filter for attenuating power line

frequencies, typically 50/60 Hz. A logic low selects this filter.

A logic high deselects or bypasses this filter. When the filter

is bypassed, the transmit frequency response extends down

to dc.

PDI

Power–Down Input (Pin 10)

This pin puts the device into a low power dissipation mode

when a logic 0 is applied. When this device is powered down,

all of the clocks are gated off and all bias currents are turned

off, which causes RO–, PO–, PO+, TG, VAG, and DT to be-

come high impedance. The device will operate normally

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connected to the VAG voltage. This minimizes transients at

the RO– pin when full–channel operation is resumed by

clocking the FSR pin. This pin is high impedance when the

device is in the powered–down mode.

Power Amplifier Input (Pin 3)

This is the inverting input to the PO– amplifier. The non–

inverting input to the PO– amplifier is internally tied to the

VAG pin. The PI and PO– pins are used with external resis-

tors in an inverting op amp gain circuit to set the gain of the

PO+ and PO– push–pull power amplifier outputs. Connect-

ing PI to VDD will power down the power driver amplifiers and

the PO+ and PO– outputs will be high impedance.

PO–

Power Amplifier Output (Inverting) (Pin 4)

chronous and approximately rising edge aligned to FST. For

optimum performance at frequencies of 1.536 MHz and

higher, MCLK should be synchronous and approximately ris-

ing edge aligned to the rising edge of FST. In many ap-

plications, MCLK may be tied to the BCLKT pin.

FST

Frame Sync, Transmit (Pin 14)

This pin accepts an 8 kHz clock that synchronizes the out-

put of the serial PCM data at the DT pin. This input is com-

patible with both Long Frame Sync and Short Frame Sync. If

both FST and FSR are held low for several 8 kHz frames, the

device will power down. FST must be clocking for the device

to power up affter being powered down by the frame syncs.

BCLKT

Bit Clock, Transmit (Pin 12)

This pin controls the transfer rate of transmit PCM data. In

the synchronous modes of sign–bit extended and receive

gain adjust, the BCLKT also controls the transfer rate of the

receive PCM data. This pin can accept any bit clock frequen-

cy from 256 to 4096 kHz for Long Frame Sync and Short

Frame Sync timing.

Data, Transmit (Pin 13)

This pin is controlled by FST and BCLKT and is high im-

pedance except when outputting PCM data. This pin is high

impedance when the device is in the powered–down mode.

FSR

Frame Sync, Receive (Pin 7)

This pin accepts an 8 kHz clock, which synchronizes the

input of the serial PCM data at the DR pin. FSR can be

asynchronous to FST in the Long Frame Sync or Short

Frame Sync modes.

BCLKR

Bit Clock, Receive (Pin 9)

This pin accepts any bit clock frequency from 256 to 4096

kHz. The BCLKR pin is also used as a mode select pin when

not being clocked for several 8 kHz frames. The BCKLT pin

is used to clock the receive PCM data transfers when the

BCLKR pin is not being clocked. When the BCLKR pinis a

logic 0, the sign–bit extended synchronous mode is selected,

which uses 16–bit transfers with the first four bits being the

sign bit. When the BCLKR pin is a logic 1, the receive gain

adjust synchronous mode is selected, which uses a 13–bit

transfer for the transmit PCM data, but uses a 16–bit transfer

for the receive side, with the 13–bit voice data being first, fol-

lowed by three bits which control the attenuation of the re-

ceive analog output.

Data, Receive (Pin 8)

This pin is the PCM data input. See the pin descriptions for

FSR, BCLKR, and BCKLT for more information.

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This is the inverting power amplifier output, which is used

to provide a feedback signal to the PI pin to set the gain of

the push–pull power amplifier outputs. This pin is capable of

driving a 300

Ω

load to PO+. The PO+ and PO– outputs are

differential (push–pull) and capable of driving a 300

Ω

load to

1.772 V peak, which is 3.544 V peak–to–peak. The bias volt-

age and signal reference of this output is the VAG pin. The

VAG pin cannot source or sink as much current as this pin,

and therefore low impedance loads must be between PO+

and PO–. The PO+ and PO– differential drivers are also ca-

pable of driving a 100

Ω

resistive load or a 100 nF Piezoelec-

tric transducer in series with a 20

Ω

resister with a smalll

increase in distortion. These drivers may be used to drive re-

sistive loads of

≥

Ω

when the gain of PO– is set to 1/4 or

less. Connecting PI to VDD will power down the power driver

amplifiers, and the PO+ and PO– outputs will be high imped-

ance. This pin is also high impedance when the device is

powered down by the PDI pin.

PO+

Power Amplifier Output (Non–Inverting) (Pin 5)

This is the non–inverting power amplifier output, which is

an inverted version of the signal at PO–. This pin is capable

of driving a 300

Ω

load to PO–. Connecting PI to VDD will

power down the power driver amplifiers and the PO+ and

PO– outputs will be high impedance. This pin is also high im-

pedance when the device is powered down by the PDI pin.

See PI and PO– for more information.

DIGITAL INTERFACE

MCLK

Master Clock (Pin 11)

This is the master clock input pin. The clock signal applied

to this pin is used to generate the internal 256 kHz clock and

sequencing signals for the switched–capacitor filters, ADC,

and DAC. The internal prescaler logic compares the clock on

this pin to the clock at FST (8 kHz) and will automatically

accept 256, 512, 1536, 1544, 2048, 2560, or 4096 kHz. For

MCLK frequencies of 256 and 512 kHz, MCLK must be syn-

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